Silicon wafers for CMOS and other integrated circuits

ABSTRACT

Manufacturing a semiconductor wafer includes growing a silicon ingot substantially uniformly doped with boron. The ingot has a resistivity in a range of about 10 to 400 milli-ohm-centimeter and is sliced into individual wafers. The wafers are heated in an atmosphere containing hydrogen at a temperature of at least about 1,000° C. so that a significant amount of boron diffuses out of a near-surface region of the wafers. For example, after heating the wafers, the resistivity of the near-surface region of the wafers can be in the range of about 0.5 to 10 ohm-centimeter. Wafers made using the foregoing technique are particularly suited for the fabrication of CMOS integrated circuits. Even in the absence of an epitaxial layer, the lighter doping of the near-surface reduced boron concentration region enables circuit fabrication while the heavier doping of the bulk region of the wafer can help prevent the occurrence of latch-up. The technique can significantly reduce the cost of CMOS fabrication.

BACKGROUND

[0001] The present invention relates generally to silicon wafers forcomplementary metal-oxide-semiconductor (CMOS) and other integratedcircuits.

[0002] As integrated semiconductor devices continue to grow incomplexity, there is a continuing need to increase the density of thesemiconductor devices. However, the increase in density can causevarious problems some of which can lead to device failure. One suchproblem is “latch-up”, which can be caused by the close proximity ofn-channel and p-channel transistors in CMOS integrated circuits. Forexample, a typical CMOS integrated circuit fabricated on a p-typesubstrate has a p-channel transistor fabricated in an n-well and ann-channel transistor fabricated in a p-well with only a short distanceseparating the wells. Such a structure inherently forms a parasiticlateral bipolar n-p-n structure and a parasitic vertical p-n-p bipolarstructure. Under certain biasing conditions, the p-n-p structure cansupply base current to the n-p-n structure, or vice-versa, causing acurrent to flow from one well to the other well. The large current candamage the integrated circuit.

[0003] One technique for reducing the incidence of latch-up is tofabricate the CMOS transistors on an epitaxial silicon wafer 10 thatincludes, for example, a lightly boron-doped epitaxial layer 12deposited on a heavily boron-doped substrate 14 (FIG. 1A). Electricalcircuit elements 16, 18 are fabricated in the top epitaxial layer 12 asshown, for example, in FIG. 1B. The heavily doped substrate 14 helpsprevent device failure that can result from latch-up and functions as aregion into which metallic impurities are trapped.

[0004] Unfortunately, these epitaxial silicon wafers can be relativelyexpensive. A substantial portion of the cost of manufacturing suchwafers is a result of formation of the lightly-doped epitaxial layer.Increased manufacturing costs also can result from the high cost ofequipment used to fabricate the epitaxial layer, the relatively lowthroughput associated with the formation of the epitaxial layer, and thecomplexity of quality control. Accordingly, it would be advantageous toreduce the manufacturing costs associated with boron-doped siliconwafers without adversely impacting circuit performance.

SUMMARY

[0005] In general, techniques for manufacturing semiconductor wafers andintegrated circuits include heating a substantially uniformlyboron-doped wafer having a resistivity in a range of about 10 to 1,000milli-ohm-centimeter. The wafer is heated in an atmosphere containinghydrogen at a temperature of at least about 1,000° C. to achieve asignificantly increased resistivity in a near-surface region of thewafer. One or more electrical circuit elements can be fabricated in thenear-surface region. Various features and advantages will be readilyapparent from the following detailed description, the accompanyingdrawings, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006]FIG. 1A illustrates an epitaxial semiconductor wafer.

[0007]FIG. 1B illustrates part of a CMOS integrated circuit fabricatedon the epitaxial semiconductor wafer of FIG. 1A.

[0008]FIG. 2 illustrates a silicon wafer according to the invention.

[0009]FIG. 3 is a graph illustrating an exemplary profile of boronconcentration in the wafer of FIG. 2 as a function of depth.

[0010]FIG. 4 is a flow chart showing steps in an exemplary process forfabricating a wafer according to the invention.

[0011]FIG. 5 illustrates further details of a wafer heat treatmentaccording to one specific implementation of the invention.

[0012]FIG. 6 is a graph showing boron concentration in several siliconwafers according to the invention.

[0013]FIGS. 7 and 8 show cross-sections of parts of exemplary CMOSintegrated circuits formed in wafers according to the invention.

DETAILED DESCRIPTION

[0014]FIG. 2 shows a boron-doped silicon wafer 20 which is suitable forthe fabrication of CMOS and other integrated circuits. The wafer 20 hasa near-surface region 22 having a significantly reduced amount of boron.The near-surface reduced boron concentration region 22 extends alongsubstantially the entire polished upper surface 26 of the wafer 20. Theconcentration of boron atoms in the near-surface region 22 is typicallygreater than zero, but significantly less than the concentration ofboron atoms in the bulk region 24, which has a substantially uniformlevel of boron doping.

[0015]FIG. 3 illustrates an exemplary profile of boron concentration andresistivity in the silicon wafer 20 as a function of distance from thepolished surface 26 of the wafer. In general, the near-surface region 22exhibits a boron concentration gradient that increases with increasingdepth, whereas the concentration of boron atoms in the bulk region 24 ofthe wafer 20 is substantially uniform. As the concentration of boronatoms decreases near the wafer surface 26, the resistivity increases.Therefore, the resistivity of the wafer 20 in the near-surface reducedboron concentration region 22 is greater than the resistivity in thebulk region 24.

[0016]FIG. 4 illustrates a process by which a wafer 20 having anear-surface reduced boron concentration region 22 can be fabricated.First, a high quality, single crystal, homogeneously boron-doped siliconingot is formed (step 30). Preferably, the doping level of boron resultsin a resistivity in the range of about 10 to 1,000 milli-ohm-centimeter(mohm-cm). In some applications, it is advantageous to provide the ingotwith a boron-doped level so that the resistivity is in a range of about100 to 400 mohm-cm. Resistivities in the range of about 30 to 70 mohm-cmalso may be particularly suitable for some applications.

[0017] A conventional Czochralski technique can be used to form theuniformly boron-doped silicon ingot, although in some implementations,other processes, such as crucible-free floating or float zonestechniques, can be used. The ingot then is sliced into individual waferswhich are subsequently lapped and polished (step 32). Standardtechniques can be used for the slicing, lapping and polishing.

[0018] The polished wafers are subjected to a heat treatment in a hightemperature furnace to cause at least some of the boron atoms to diffuseout of the near-surface region 22 (step 34). In exemplary heattreatments, the polished wafers are heated at temperatures in the rangeof about 1,000 celsius (° C.) to about 1,250° C. The heat treatment canbe performed, for example, in an atmosphere containing hydrogen for aduration of about 1 to about 5 hours. The amount of hydrogen gas in thefurnace can vary from as little as about 5% to as much as 100%. Thehydrogen gas is an active gas that reacts with the boron atoms in thewafer 20. If less than about 100% hydrogen gas is used, a mixture ofhydrogen gas and a neutral gas, such as argon, can be used. Boron thatdiffuses out of the wafer 10 can combine with the hydrogen to form agaseous byproduct which is swept out of the furnace.

[0019] The annealed wafers can then be used for device and circuitfabrication (step 36).

[0020]FIG. 5 illustrates further details of the heat treatment accordingto one specific implementation. A batch of about 100 to 150 polishedwafers are loaded into a vertical diffusion furnace maintained at atemperature of about 600° C. (step 40). The furnace temperature isgradually increased. First, the furnace temperature is increased toabout 800° C. at a rate of approximately 40° C./minute (step 42). Next,the furnace temperature is increased from 800° C. to about 900° C. at arate of approximately 20° C./minute (step 44). The furnace temperatureis then increased to about 1,000° C. at a rate of approximately 10°C./minute (step 46). Subsequently, the furnace temperature is increasedto about 1,100° C. at a rate of approximately 5° C./minute (step 48).The furnace temperature is then increased to a temperature of about1,200° C. at a rate of approximately 2° C./minute (step 50). Theforegoing sequence, in which the furnace is heated at a deceleratedrate, requires about ninety minutes to heat the furnace.

[0021] Once the furnace is heated to 1,200° C., the temperature of thefurnace is maintained at that temperature for a duration of 1-4 hours tocause boron to diffuse out of the near-surface region of the wafers(step 52).

[0022] Following the heat treatment, the furnace is cooled to about 600°C. by reversing the heating cycle described above in steps 42, 44, 46,48 and 50 (step 54). In other words, the cooling rate is accelerated asthe furnace temperature approaches 600° C. Once the furnace temperaturereaches about 600° C., the wafers can be removed from the furnace (step56).

[0023] The ramped heating sequence described above can help preventdeformation or warping of the wafers, which can result if the furnace isheated too quickly. However, other temperatures and temperaturesequences can be used to cause a substantial amount of boron to diffuseout of the near-surface region of the wafers. For example, in somecases, the furnace temperature may be increased at a substantiallyconstant rate, or the furnace may be cooled at a substantially constantrate. In general, the furnace need not be cooled using the reversesequence used to raise the furnace temperature. In many applications,the furnace can be cooled at a more rapid rate than the rate at whichthe furnace is heated. Other types of furnaces may be used forperforming the heat treatment.

[0024]FIG. 6 is a graph showing boron concentration in several siliconwafers as a function of depth from the wafer surface. One pair of waferswas prepared from a silicon ingot having a boron concentration thatresulted in a resistivity in the range of about 30-50 mohm-cm. One ofthe two wafers was annealed at a temperature of about 1,200° C. forapproximately two hours. The second of the two wafers was annealed at1,200° C. for about four hours. A second pair of wafers was preparedfrom a silicon ingot having a boron concentration that resulted in aresistivity in the range of about 50-70 mohm-cm. One of the two waferswas annealed at a temperature of about 1,200° C. for approximately twohours, whereas the second wafer was annealed at 1,200° C. for about fourhours. Each of the wafers was annealed in an atmosphere of about 100%hydrogen.

[0025] The boron concentration data in FIG. 6 was obtained throughsecondary ion mass spectroscopy (SIMS) analysis. As can be seen from thegraph in FIG. 6, the wafers exhibit a boron concentration gradient inwhich the boron concentration is significantly less in the near-surfaceregion compared to the boron concentration in the bulk of the wafer.Therefore, the resistivities near the surface of the wafers are higherthan in the bulk regions of the wafers.

[0026] In general, it is desirable to use a wafer obtained from an ingothaving a boron concentration level such that, following the wafer heattreatment, the near-surface region of the wafer has a resistivity in therange of about 0.5 to 10 ohm-centimeter (ohm-cm). The heat treatment canresult in a near-surface region of the wafer having a boronconcentration about an order of magnitude less than the boronconcentration in the bulk of the wafer. Generally, the boron gradientincreases with increasing depth from the surface to a depth in the rangeof about 0.1 to 1.0 μm. For applications such as the fabrication of CMOSintegrated circuits, the depth of the near-surface reduced boronconcentration region should be on the order of about at least 0.2 μm.

[0027] A wafer 20 fabricated according to the technique described aboveis suitable for the fabrication of integrated circuits that can benefitfrom a structure in which electrical circuit elements are formed in thenear-surface reduced boron concentration region 22. As shown in FIG. 7,circuit elements such an n-channel MOS transistor 70 and a p-channel MOStransistor 72 can be formed in the near-surface region 22 using standardfabrication techniques. The n-channel transistor 70, which includes agate 82, a gate dielectric 84 and doped regions 86, 88, is formed in ap-type well 78. An n-type well region 76 is provided for the p-channeltransistor which includes a gate 94, a gate dielectric 96 and dopedregions 98, 100. The NMOS and PMOS transistors 70, 72 are separated by ashallow trench isolation region 74. Metallization or other conductivecontacts 102 are provided for the N+ and P+ gates and the doped regions.The devices 70, 72 are exemplary only and other devices also can beformed on the wafer 20.

[0028] Several advantages can be obtained by fabricating the CMOSintegrated circuit in the wafer 20 (FIG. 7) rather than the epitaxialwafer 10 (FIG. 1B). As previously mentioned, the overall cost offabrication can be reduced by eliminating the need to form an epitaxiallayer on the semiconductor wafer. The reduction in manufacturing costscan be particularly significant with respect to large wafers, forexample, 300 millimeter (mm) wafers.

[0029] Fabricating devices on a wafer 20 can still provide some of theadvantages of an epitaxial wafer. For example, the lighter doping of thenear-surface reduced boron concentration region 22 enables circuitfabrication while the heavier doping of the bulk region 24 of the wafercan help prevent the occurrence of latch-up.

[0030] In addition, the heat treatment can cause oxygen to diffuse outof the near-surface region and can cause the precipitation of oxygenparticles in the bulk region of the wafer. Precipitation of oxygen inthe bulk region helps trap metal impurities in the wafer. In addition,the heat treatment can result in wafers having fewer point defects inthe near-surface region. Trapping metal impurities in the silicon wafersand reducing the number of defects prior to device fabrication isincreasingly important because of the relatively high temperaturesrequired to achieve those features. Assuming that the current trendtoward the use of lower temperatures for device fabrication continues,the ability to trap metal impurities and reduce the number of defectsprior to device fabrication may obviate the need to perform subsequenthigh temperature processes during device fabrication.

[0031] In some applications it is possible to eliminate the step offorming a p-type well 78 in the near-surface reduced boron concentrationregion 22 during fabrication of the NMOS transistor 70 in the wafer 20(see FIG. 8). That is because the near-surface region 22 remains lightlydoped with boron atoms even after the heat treatment. As a result, atleast one implant step can be eliminated in some implementations duringCMOS integrated circuit fabrication.

[0032] Other implementations are within the scope of the followingclaims.

What is claimed is:
 1. A method of manufacturing a semiconductor wafer,the method comprising: growing a silicon ingot substantially uniformlydoped with boron, wherein the ingot has a resistivity in a range ofabout 10 to 1,000 milli-ohm-centimeter; slicing the ingot intoindividual wafers; and heating at least one of the wafers in anatmosphere containing hydrogen at a temperature of at least about 1,000°C. to achieve a significantly increased resistivity in a near-surfaceregion of the at least one of the wafers.
 2. The method of claim 1wherein the at least one of the wafers is heated to achieve aresistivity in the near-surface region in a range of about 0.5 to 10ohm-centimeter.
 3. The method of claim 2 wherein the near-surface regionwith the significantly increased resistivity has a thickness of at least0.2 micron.
 4. The method of claim 3 wherein the at least one of thewafers is heated at a temperature of approximately 1,200° C. duringheating.
 5. The method of claim 3 wherein heating the at least one ofthe wafers takes place in an atmosphere having at least about 5%hydrogen.
 6. The method of claim 3 wherein the heating is performed inan atmosphere consisting essentially of a neutral gas and at least about5% hydrogen.
 7. The method of claim 2 further including fabricating oneor more electrical circuit elements in the near-surface region after theheating.
 8. The method of claim 1 wherein the heating includes raisingan ambient temperature from an initial temperature to the temperature ofat least about 1,000° C. in a plurality of stages in which the rate atwhich the temperature is increased during each stage is less than therate at which the temperature is increased during a previous stage. 9.The method of claim 1 wherein the at least one of the wafers is heatedat a temperature of at least 1,000° C. for at least about one hour. 10.The method of claim 1 wherein the ingot has a resistivity in a range ofabout 30 to 70 milli-ohm-centimeter, and wherein the at least one of thewafers is heated at a temperature of at least about 1,000° C. for atleast about two hours.
 11. The method of claim 1 wherein the ingot has aresistivity in a range of about 30 to 70 milli-ohm-centimeter, andwherein the at least one of the wafers is heated at a temperature of atleast about 1,000° C. to achieve a resistivity in a near-surface regionof the wafer in a range of about 0.5 to 10 ohm-centimeter.
 12. Themethod of claim 1 wherein the ingot has a resistivity in a range ofabout 100 to 400 milli-ohm-centimeter, and wherein the at least one ofthe wafers is heated at a temperature of at least about 1,000° C. toachieve a resistivity in a near-surface region of the wafer in a rangeof about 0.5 to 10 ohm-centimeter.
 13. The method of claim 11 furtherincluding fabricating one or more electrical circuit elements in thenear-surface region after the heating.
 14. A method of manufacturing asemiconductor wafer, the method comprising: growing a silicon ingotsubstantially uniformly doped with boron, wherein the ingot has aresistivity in a range of about 10 to 1,000 milli-ohm-centimeter;slicing the ingot into individual wafers; polishing a surface of atleast one of the wafers; heat treating the at least one wafer in anatmosphere containing hydrogen at a temperature of at least about 1,000°C. to achieve a resistivity in a region near the polished surface of thewafer in a range of about 0.5 to 10 ohm-centimeter.
 15. A method ofmanufacturing a semiconductor integrated circuit, the method comprising:heating a substantially uniformly boron-doped wafer in an atmospherecontaining hydrogen at a temperature of at least about 1,000° C. toachieve a significantly increased resistivity in a near-surface regionof the at least one wafer, wherein prior to the heating, the wafer has aresistivity in a range of about 10 to 1,000 milli-ohm-centimeter; andfabricating at least one electrical circuit element in the near-surfaceregion.
 16. The method of claim 15 wherein, after the heating, thenear-surface region has at resistivity in a range of about 0.5 to 10milli-ohm-centimeter.
 17. The method of claim 16 wherein after theheating, the resistivity of a bulk region of the wafer is significantlyless than the resistivity in the near-surface region.
 18. The method ofclaim 16 wherein the near-surface region has a thickness of at leastabout 0.2 micron, and wherein the fabricating includes forming a CMOSintegrated circuit in the near-surface region.
 19. The method of claim16 including fabricating an n-channel MOS device in the near-surfaceregion without performing a p-well implant for the n-channel MOS device.20. The method of claim 16 wherein, prior to the heating, the wafer hasa resistivity in a range of about 30 to 70 milli-ohm-centimeter.
 21. Themethod of claim 16 wherein, prior to the heating, the wafer has aresistivity in a range of about 100 to 400 milli-ohm-centimeter.
 22. Themethod of claim 16 wherein the heating includes heating the wafer at atemperature of at least 1,200° C. for at least about two hours.
 23. Themethod of claim 16 wherein the heating is performed in an atmospherecontaining at least about 5% hydrogen.
 24. The method of claim 16wherein the heating is performed in an atmosphere consists essentiallyof a neutral gas and at least about 5% hydrogen.
 25. A siliconsemiconductor wafer comprising: a polished surface; a substantiallyuniformly boron-doped bulk region having a resistivity in a range ofabout 10 to 1,000 milli-ohm-centimeter; and a reduced boronconcentration layer near the polished surface, wherein the reduced boronconcentration layer extends along substantially the entire polishedsurface and has a boron gradient that increases with increasing depthfrom the polished surface to a depth in a range of about 0.1 to 1.0,wherein the reduced boron concentration layer has a resistivity in arange of about 0.5 to 10 ohm-centimeter.
 26. The semiconductor wafer ofclaim 25 wherein the reduced boron concentration layer has a borongradient wherein the resistivity decreases with increasing distance fromthe polished surface.
 27. The semiconductor wafer of claim 25 whereinthe bulk region has a resistivity in a range of about 30 to 70milli-ohm-centimeter.
 28. The semiconductor wafer of claim 25 whereinthe bulk region has a resistivity in a range of about 100 to 400milli-ohm-centimeter.
 29. The semiconductor wafer of claim 25 whereinthe near-surface reduced boron concentration layer has a thickness of atleast about 0.2 micron.
 30. A method of fabricating an integratedcircuit, the method comprising: forming at least one electrical circuitelement in a reduced boron concentration layer near a surface of asilicon wafer, wherein the wafer includes a substantially uniformlyboron-doped bulk region having a resistivity in a range of about 10 to1,000 milli-ohm-centimeter, and wherein the reduced boron concentrationlayer has a boron gradient that increases with increasing depth from thesurface to a depth in a range of about 0.1 to 1.0, and wherein thereduced boron concentration layer has a resistivity in a range of about0.5 to 10 ohm-centimeter.
 31. The method of claim 30 wherein the bulkregion has a resistivity in a range of about 30 to 70milliohm-centimeter.
 32. The method of claim 30 wherein the bulk regionhas a resistivity in a range of about 100 to 400 milli-ohm-centimeter.33. The method of claim 30 wherein the near-surface reduced boronconcentration layer has a thickness of at least about 0.2 micron.